Quantum arithmetic computation requires a substantial number of scratch qubits to stay reversible.These operations necessitate qubit and gate resources equivalent to those needed for the larger of the input or output registers due to state encoding.Quantum Hamiltonian Computing (QHC) introduces a novel approach by encoding input for logic operations within a single rotating quantum gate.This innovation reduces the required qubit register N to the size of the output states O, where N = log 2 O. Leveraging QHC principles, we present reversible half-adder and full-adder circuits that compress the standard Toffoli + CNOT layout [Vedral et al., PRA, 54, 11, (1996)] from three-qubit and four-qubit formats for the Quantum half-adder circuit and five sequential Fredkin gates using five qubits [Moutinho et al., PRX Energy 2, 033002 (2023)] for full-adder circuit; into a two-qubit, 4×4 Hilbert space.This scheme, presented here, is optimized for classical logic evaluated on quantum hardware, which due to unitary evolution can bypass classical CMOS energy limitations to certain degree.Although we avoid superposition of input and output states in this manuscript, this remains feasible in principle.We see the best application for QHC in finding the minimal qubit and gate resources needed to evaluate any truth table, advancing FPGA capabilities using integrated quantum circuits or photonics.
This paper presents a novel approach to quantum arithmetic operations using Quantum Hamiltonian Computing (QHC), which aims to reduce the qubit overhead required for reversible logic by encoding classical inputs within a single quantum gate. The authors introduce reversible half-adder and full-adder circuits that operate with only two qubits in a 4x4 Hilbert space, significantly lowering resource requirements compared to traditional methods that utilize larger qubit registers. The paper discusses the limitations of needing scratch qubits for reversibility and outlines how the QHC paradigm minimizes energy consumption while maintaining functionality. The proposed circuits demonstrate the potential for advancements in integrated quantum circuits and photonics, highlighting a practical avenue for overcoming the energy limitations of classical CMOS designs.
This paper employs the following methods:
- Quantum Hamiltonian Computing (QHC)
The following datasets were used in this research:
- Presented two-qubit half-adder and full-adder circuits in a 4x4 Hilbert space, requiring fewer resources than traditional designs.
The authors identified the following limitations:
- Current design does not utilize superposition of input and output states; requires further optimization to increase expressiveness of unitary maps.
- Number of GPUs: None specified
- GPU Type: None specified
- Compute Requirements: None specified